it may be required. Below is a table that is available from IEEE802.3 25Gb/s Ethernet study group that helps to summarize the length advantage when enabling FEC versus the latency penalty. There are some customers who consider the 250ns for latency for the Clause 91 RS-FEC to be unacceptable. But depending how much margin may be in the PCB design, some engineers would suggest that there is too much guardband in the IEEE specification to handle some of the older package technologies, so using thicker conductors in the DAC passive cable (26 AWG) with moderate or no FEC, 5M cable lengths for passive DAC may be achievable. I hope to attend the next Plug fest at UNH IOL and gain more insight!
Another interesting table that helps to clean up some of the confusion is the nomenclature versus clause correlation table, showing what is optional and what is mandatory. This is also available from the working group presentations and shows for the 100GBASE-CR4 Clause 91 RS-FEC as being mandatory for the lengths that we would like to support (5 Meters).
After beginning to understand some of the specifications, I started digging into new designs and testing on a 100G port switch. Running eye scans using the internal MAC software, one can optimize the TX pre-emphasis and main, or you can choose to utilize the auto-tuning features often available in the newest ASICS. By looping one port back into another with a short loopback DAC, I can avoid the test fixtures that are not always available to drive directly into my oscilloscope. In the past, I have utilized a Wilder test fixture to break out the 10G and 40G SFP+/QSFP+ to drive directly into my scope and optimize TX main and pre-emphasis by intelligently tweaking the TX driver settings. More recenty, we have been relying on the eyescan features of the MAC to help perform this task. Below is a sample eye diagram from an ASIC eyescan report.
After I accumulate and verify models into my network/channel simulation tools (i.e. SiSoft’s QCD), I import the physical design. Then I generate masks from the IEEE specs and run post layout simulations on every high speed channel on my PCB, making sure to have critical stackup electrical parameters (Df, Dk, CU roughness) defined and previously verified. I can run hundreds of simulations quickly and examine worst case networks and optimize in the layout or verify they are adaquate. I also make sure to properly define VIA stubs and insure the layout meets all of the semiconductor vendors’ design rules.
Robert Haller , senior principal hardware engineer for Extreme Networks, is working on next generation Ethernet switching solutions, is the corporate Signal and Power Integrity lead and has been a member of the DesignCon Technical Program Committee for 16 years.