includes implanted DFT within an already constrained schedule. It brings two changes to the usage of a hardware emulator –– a change in the compilation flow and a change in run-time execution.
First, the hardware emulation’s compiler reads a gate-level design instrumented with the DFT structure together with a IEEE Standard Test Interface Language (STIL) format file including design I/O configuration, clock information and test vectors. The compiler creates an infrastructure for reading test vectors from the STIL file.
While hardware emulation performs at orders of magnitude faster speed than simulation, the DFT App verifies DFT patterns by four or five orders of magnitude. In practical terms, three-months-worth of simulation, or 2,160 hours, can be accomplished in less than an hour.
|The DFT (design for testability) app offers performance advantages over traditional simulation .|
A hardware emulator provides enough power to keep the DFT verification schedule on track, increasing yield and accelerating both TTM and TTE, ultimately boosting profits. It broadens hardware emulation’s use model, improves performance and helps a verification engineer avoid risk and ensure quality chips delivered to customers.
Dr. Lauro Rizzatti ( [email protected]) is a verification consultant and industry expert on hardware emulation. He has held positions in management, product marketing, technical marketing, and engineering.